Learn VLSI with VHDL Programming Development
Ogma TechLab offers professional Development Courses for recent graduates and post-graduates in Electronics/Electrical/Telecommunications engineering. This program is specially designed with an objective to provide a sound platform for the students and prepare them for a successful career in the fields of VLSI Designs and verification and FPGAs.
Course Objectives
This course is structured to build upon Digital electronics subject which is highly modular with each module provide comprehensive training on specific aspect of the VLSI Design flow. The Advanced Diploma in VLSI Design & Technology program is designed and delivered by VLSI Industry experts with decades of experiences in the VLSI Industry. This course is structured to impart an extensive VLSI Training to raw engineers with background in Digital Electronics or basic VLSI for undergraduates or post-graduates studies.Curriculum
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Lecture 1SSI, MSI, LSI, VLSI
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Lecture 2Real Time Applications
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Lecture 3Current Control Vs Voltage Control Device
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Lecture 4Design Challenges
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Lecture 5System Level Requirements
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Lecture 1Design Flow of VLSI
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Lecture 2Y Chart in VLSI
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Lecture 3FPGA
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Lecture 3ASIC
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Lecture 3VLSI Applications
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Lecture 1NMOS, PMOS, CMOS Gates
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Lecture 2Effect Of Capacitive Loading
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Lecture 1Transistor Sizing For Performance
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Lecture 1CMOS Power Consumption
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Lecture 1Low Power Design Techniques
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Lecture 1Switching Characteristics of CMOS
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Lecture 1CMOS Interconnection Delays
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Lecture 1MOSFET Capacitance
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Lecture 1NAND Gate, AND Gate
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Lecture 2NOR & OR Gate
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Lecture 3XOR & X-NOR
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Lecture 4Design for Boolean expression
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Lecture 5Alternative to if else statements
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Lecture 6Switch case statement
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Lecture 7goto statements
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Lecture 1Gate Design
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Lecture 2Multiplexer
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Lecture 3Decoder
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Lecture 4Encoder
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Lecture 5Boolean Expression
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Lecture 1Basic idea on digital electronics
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Lecture 2Circuit making using gates
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Lecture 3Combinational logic circuits
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Lecture 4Flip-flop
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Lecture 5Latch
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Lecture 6Counter
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Lecture 7Register
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Lecture 1Entity and Architecture
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Lecture 2VHDL Component
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Lecture 3VHDL Designing Hierarchies
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Lecture 1Signal Assignment
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Lecture 2Concurrency
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Lecture 3When and with statements
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Lecture 4Behavioral Model
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Lecture 5Generics
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Lecture 6Data Types
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Lecture 6Vector Assignments
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Lecture 1Process Statement
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Lecture 2If Statement/Case Statement
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Lecture 3Multiple Assignment
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Lecture 4Wait Statement
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Lecture 5Loop Statements
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Lecture 1Libraries
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Lecture 2Packages
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Lecture 3Procedures
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Lecture 4Functions
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Lecture 1Component Declaration
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Lecture 2Port map
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Lecture 3Generic map
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Lecture 4Configuration
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Lecture 5Components in a package
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Lecture 1Different forms of test bench
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Lecture 2Text IO
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Lecture 1Introduction of Micro wind
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Lecture 2Design of CMOS inverter
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Lecture 3NAND & NOR Gate
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Lecture 4Boolean expression design
